|ARM Technical Support Knowledge Articles|
Applies to: Cortex-M7
This Knowledge Article applies to engineers at companies which have licensed the Cortex-M7 processor Verilog RTL for use in System-on-Chip designs.
The Cortex-M7 processor RTL is delivered together with an optional capability for the licensee to generate an obscured simulation model of the configured processor, called a Design Simulation Model (DSM), which may be used for distribution in-house and to end-customers, for the purpose of simulating the chip design containing that processor configuration, without exposing the content of that processor IP to the wider audience.
The messages referred to in the article title might be produced for wildcards with extensions such as: *.bin *.elf *.rcf *.inc *.disass
These messages are a harmless side-effect of some checks which were included in the script during its development, and were intended to be removed before release. Their removal was overlooked, so they are present in versions including r1p1-00rel0 (current at the time of writing this article). The intention is to remove the checks from future versions, in order to eliminate those redundant messages.
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