ARM Technical Support Knowledge Articles

Why do DTCM RAM blocks need to have the same wait state behavior?

Applies to: Cortex-M7


This Knowledge Article applies to chip designers who are configuring a Cortex-M7 instance to include Tightly-Coupled Memory in their chip.

The documentation for this procedure states that:

"The DTCM RAMs must use identical configurations. This means they must be the same size and have the same wait state behavior."

Does this mean that the D*TCMWAIT signals need to be identical at all times?


The RAM blocks need to have the same fundamental cycle timing for the purpose of MBIST testing of the RAM.

In functional mode, external logic may assert different wait states on the two halves of the RAM, for example during soft error correction, so the D*TCMWAIT signals do not need to be identical in normal use.

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