|ARM Technical Support Knowledge Articles|
The Knowledge Article is intended for chip designers who have licensed the Cortex-M3 or Cortex-M4 processor IP and are designing a chip containing the processor and are providing external debug access as a feature of the chip. For end-users who are working with an off-the-shelf chip containing one or more of these processors, the answer to this question should be available in the product documentation for the chip, as provided by the chip vendor.
These processors are designed to support the CoreSight debug standard via a Debug Access Port (DAP) conforming to the "ARM Debug Interface Architecture Specification ADIv5.0 to ADIv5.2" (ADIv5.2). A DAP consists of a front end Debug Port (DP) component supporting one or more external pin protocols for the connection to the debugger, and one or more Access Port (AP) components, driving an on-chip bus or other on-chip connection to debuggable components and/or memory systems. The DP connects to the AP(s) via a DAP Bus.
The DP is typically one of:
- JTAG-DP, supporting the standard IEEE 1149.1 JTAG protocol
- SW-DP, supporting ARM's Serial Wire Debug protocol defined in the ADIv5.2
- SWJ-DP, supporting run-time switching between each of the above protocols
For Cortex-M3 and Cortex-M4, the AP is contained within the processor instance, so the debug slave connection at the processor boundary is a DAP Bus slave interface.
The processor is provided together with an example integration, including an SWJ-DP which is optionally configurable as just an SW-DP.
The SWJ-DP delivered with the Cortex-M3 r2p1 and Cortex-M4 r0p1 complies to the DPv1 architecture, and does not therefore support Multi-drop capability.
Since the processor's debug slave interface is a standard DAP Bus slave interface, the processor can be successfully integrated with any version of DP, and with any DAP implementation which exposes a master port directly from its DAP Bus.
ARM's recommended solution for implementing Cortex-M3 or Cortex-M4 with advanced features such as Multi-drop SWD is to license the TM100 "CoreSight SoC-400" (CSSoC) IP which includes the capability to generate a customized DAP to match a specific chip's requirements, including DPv2 support for Multi-drop SWD.
For multi-processor chip designs including either of these processors (or Cortex-M0), it is useful in addition to license TM112 "CoreSight SoC LIB400-M" which provides a suitable integration level for direct integration of these three processors into a multi-processor debug and trace infrastructure using CSSoC.
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