|ARM Technical Support Knowledge Articles|
The Knowledge Article is relevant to chip designers simulating an RTL model of a chip containing a Cortex-M3 or Cortex-M4 processor.
The ETM interface signals can provide useful information during RTL simulation. For example, by tracing ETMIVALID it is possible to identify each cycle in which an opcode is executed. The address of the opcode being executed can be seen by tracing ETMIA[31:1]. (The usability of this trace can be increased by grouping ETMIA[31:1] with a constant 1'b0 signal, for example FIXMASTERTYPE or similar, to re-align the 31-bit signal into a 32-bit field so that a hexadecimal representation matches the actual address of the opcode.) The address can be cross-referenced against a disassembly listing of the executable code image, generated, for example via the "fromelf" command from the ARM toolchain: eg. fromelf --text --output <myprog>.dis -c -v <myprog>.elf
The ETM interface (irrespective of the presence or absence of the ETM itself) can be enabled by clearing bit "ETM Power Down" of the ETM Main Control register, ETMCR, at address 0xE0041000. This can be done directly from the Debug Port, but in order to do this from code running on the processor, it is necessary to first unlock the ETM for processor access. This is achieved by clearing bit of the ETM Lock Access Register, ETMLAR, at address 0xE0041FB0.
*ETMLAR = 0xC5ACCE55; *ETMCR &= 0xfffffffe;
Note that activation of the ETM interface signals does not depend upon bit of the Debug Exception and Monitor Control Register, DEMCR.TRCENA
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