|ARM Technical Support Knowledge Articles|
Applies to: Cortex-M7
This Knowledge Article is relevant to chip designers integrating a Cortex-M7 with Tightly Coupled Memories (TCM) in their chip design.
The processor provides some signals for management of TCM accesses, for example xTCMERR (ITCMERR or DTCMERR) and xTCMRETRY (ITCMRETRY or DTCMRETRY).
That is not the expected use case of xTCMERR.
xTCMERR indicates a non-fixable error such as a privilege violation. It will be treated as an abort.
An ECC error should be signaled by xTCMRETY, allowing the processor to re-play that access. Meanwhile the external ECC logic can repair the soft error.
Errors returned from speculative accesses would be ignored, as stated in the Technical Reference Manual: "If an access is speculative, the processor ignores any error or retry signaled for the access"
Did you find this article helpful? Yes No
How can we improve this article?