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What is the structure of the debug ROM tables in Cortex-M7 ?

Applies to: Cortex-M7


Chip designs containing ARM processors are often configured to allow connection of an external debugger through a Debug Access Port, to allow the user to perform debug of code running on the processor.

The debug capabilities conform to ARM's CoreSight standard, and the Debug Access Port (DAP) conforms to the ARM Debug Interface v5 Architecture Specification. These standards provide a method for the external debug tools to locate and identify the debug-related functionality included in the chip.

A DAP consists of one Debug Port (DP) component, supporting one or more debug protocols on the external pin interface of the chip (typically JTAG or Serial Wire Debug protocol), and one or more Access Port (AP) components, providing access to bus systems in the chip. Each AP for an addressable bus protocol such as APB, AHB or AXI contains a BASE register which may indicate the address of the starting point of the debug infrastructure behind that AP. The starting point is typically a debug ROM table, providing pointers to addresses of other debug-related components within that subsystem.

The Cortex-M7 provides an AHB-Lite debug interface, suitable for connection to an AHB-AP in the DAP.

The ARMv7-M architecture, to which Cortex-M7 conforms, specifies a requirement for a debug ROM table at a fixed address in the processor's memory map and containing a predefined minimal set of optional ROM table entries. The CoreSight architecture allows for this debug ROM table to be part of a larger and more flexible hierarchical system of debug ROM tables.


The "PPB ROM Table" at 0xe00ff000 is the ARMv7-M architected ROM table, with the architecturally prescribed entries. The Cortex-M7 design has chosen to upwardly delegate responsibility for a couple of those entries, the TPIU and the ETM, so these are marked "not present" at this level.

Instead, the ETM entry is provided in the "Processor ROM Table" based at 0xe00fe000 in the CORTEXM7INTEGRATIONCS level (the minimal level at which the chip designer is authorized to instantiate a Cortex-M7 in their chip design). This ROM Table must contain a pointer to the architectural ROM Table, and also points to the Cross-Trigger Interface (CTI) component, if present.

This construction means that the ROM table hierarchy more closely aligns with the logical hierarchy of the top level CORTEXM7INTEGRATIONCS and the subsidiary CORTEXM7 levels of the processor design.

As both of these ROM tables are within the CORTEXM7INTEGRATIONCS boundary, they are not licensee (chip designer) modifiable.

The licensee may choose to implement an additional System level ROM table, to include a reference to a Trace Port Interface Unit (TPIU) and/or other components which are outside of the CORTEXM7INTEGRATIONCS level, but controlled locally through the same AHB-AP. A System level ROM table also allows the chip designer to insert their unique chip identification information in the PeripheralID registers of this ROM table. This ROM table can occupy any arbitrary 4kB address block in the AHB-AP's memory map. If a System level ROM table is used, it must contain an entry pointing to the "Processor ROM Table".

In the example CM7IKMCU delivered with the processor RTL, the System level ROM table happens to be placed at address 0xe00fd000 on the Private Peripheral Bus, though it could just as well have been placed at any other address in the memory system, eg. 0xf0000000.

Identification information is taken from the Top Level ROM Table. The Top Level ROM Table is defined to be the one which the debugger finds behind a Mem-AP (AHB-AP, APB-AP, AXI-AP), pointed to by that AP's BASE register. The BASE register of the Cortex-M7's AHB-AP in the DAP therefore contains the address of the System level ROM Table, if present, or the Processor ROM Table, if there is no system level ROM table.

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