|ARM Technical Support Knowledge Articles|
Applies to: Cortex-M7
The Cortex-M7 processor is designed to handle interrupts from synchronous sources, in the same clock domain as the processor itself.
Cortex-M7 documentation from ARM which describes, for example, expected interrupt latency, is based on this assumption.
Chip designers who are using Cortex-M7 in their chip designs, and who are connecting interrupt signals from sources in other clock domains, are required to add external synchronizers between the device which is requesting the interrupt and the processor input, to ensure that the interrupt signal is correctly synchronized at the processor input.
A synchronizer is typically composed of two flip-flops, back-to-back, typically resulting in an additional two processor clock cycles of latency between the event which triggers the interrupt and the interrupt being recognized by the processor.
End users of chips containing Cortex-M7 processors should be able to obtain chip-specific documentation of these implementation details, where relevant, from the chip vendor.
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