|ARM Technical Support Knowledge Articles|
Non-confidential programmers' level documentation for many ARM processor and other IP blocks, and architecture specifications, can be obtained via ARM's infocenter.arm.com website. These include:
- CoreSight on-chip trace and debug -> Architecture Specifications -> Embedded Trace Macrocell (ETMv3) Architecture Specification [ARM IHI 0014]
- Cortex-M series processors -> Cortex-M4 -> Revision: r0p1 -> CoreSight ETM-M4 Technical Reference Manual [ARM DDI 0440]
- Cortex-M series processors -> Cortex-M3 -> Revision: r2p1 ->ARM Cortex-M3 Processor Technical Reference Manual [ARM 100165]
This article refers to discrepancies which may be observed between some editions of these documents. At the time of writing, these editions are: ARM IHI 0014Q, ARM DDI 0440C and ARM 100165_0201_00_en.
In addition, chip designers who have licensed the Cortex-M3 processor with ETM-M3 for inclusion in their chip designs will have received, along with the processor design RTL description, and example system design in which they can run and/or modify a number of test programs which allow the behavior of the IP to be observed in logic simulation.
On close examination, some of these test programs are seen to exhibit some of these discrepancies, although they do not generally affect the successful completion of the tests.
The ETM Architecture Spec defines an architectural list of memory-mapped registers from which the current state of the ETM can be read and to which ETM configuration settings can be written. In many cases, the ETM Architecture Spec does not clearly indicate which registers and fields within registers are mandatory, and which registers and fields are optional for a particular processor's ETM to implement.
The ETM implementations for the Cortex-M family processors are optimized for microcontroller applications, meaning that they implement a subset of the full ETM capability.
The Cortex-M3 TRM and the ETM-M4 TRM define a subset of the architectural register set representing the registers and fields which are actually implemented in the ETM-M3 and ETM-M4.
Both TRMs contain a typographical error indicating that the FIFOFULL Level Register, ETMFFLR, is located at address 0xE0041028. However, this register is actually located at address 0xE004102C, corresponding to the architectural description of ETMFFLR as Register 0x00B (offset 0xB words, or 0x2C bytes, within the 4kB address range of the ETM).
Some IP-XACT views of these processors reproduce the same error.
The ETM Architecture Spec proposes the following programming configuration for the ETM:
"Tracing all memory
To trace all memory:
• set bit  in register 0x009, the ETMTECR1, to 1
• set all other bits in register 0x009, the ETMTECR1, to 0
• set all bits in register 0x007, the ETMTECR2, to 0
• set register 0x008, the ETMTEEVR, to 0x6F (TRUE)."
However, in the case of ETM-M3 and ETM-M4, ETMTECR1 bit is reserved, and ETMTECR2 is not implemented. In reality, the current revisions of the ETMs ignore the write to ETMTECR1 bit, but it would be better design practice to avoid writing '1' to Reserved bits, and avoid writing to unimplemented registers, where possible.
For chip designers using Cortex-M3 and ETM-M3 in their chip designs, the two example ".cdapml" programs in the ./example/Software/. directory also make some architecturally erroneous writes to the ETM registers. (Note that the Cortex-M3 Integration and Implementation Manual [IIM] explicitly defines the test programs as being modifiable by the user.)
In particular, the above mentioned write to set ETMTECR1 bit is implemented, and there is also a write to the Synchronization Frequency Register, ETMSYNCFR, at address 0xE00411E0, which is defined to be Read-only in the Cortex-M3.
In fact, the EtmCompare script which is (optionally) used in running these tests, keys some of its behavior off programming accesses from the processor to the ETM-M3. One such access is the write to the ETMTECR1, so for the purpose of getting the EtmCompare script to run correctly, it is necessary to retain a valid programming write to the ETMTECR1. A write data value of 0x00000000 is suitable for this purpose.
The access to ETMSYNCFR is entirely superfluous in this context, and may be omitted.
Therefore the section of DAPML programming for the ETM may be modified to:
... DAP_WRITE_AP CM3 0x0c 0x0000006F DAP_WRITE_AP CM3 0x04 0xE0041024 SNO DAP_WRITE_AP CM3 0x0c 0x00000000 DAP_WRITE_AP CM3 0x04 0xE004102C SNO DAP_WRITE_AP CM3 0x0c 0x00000000 ;DAP_WRITE_AP CM3 0x04 0xE00411E0 SNO ;DAP_WRITE_AP CM3 0x0c 0x00000400 DAP_WRITE_AP CM3 0x04 0xE00411F0 SNO ...
Did you find this article helpful? Yes No
How can we improve this article?