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Cortex-M0 Integration Kit config_check reports "DBG: 0 (Expected 1) - FAIL" when DBG is set

Applies to: Cortex-M0


This Knowledge Article is relevant to chip designers who have licensed the ARM Cortex-M0 processor RTL for inclusion in their chip design. At the time of writing, the currently released version of Cortex-M0 is r0p0-03rel2.

The RTL description of the processor is delivered to licensees together with an example MCU design, a testbench, and some test programs, known as the Integration Kit, or IK.

The processor design offers a number of optional features for the chip designer to select. Once the chip designer has selected the desired configuration, the IK tests should be run to verify that the configuration has been specified correctly.

One of the tests, called "config_check", is intended to perform a kind of two-factor authentication to ensure that the actual configuration specified matches correctly with a separately recorded indication of the expected configuration.

The expected configuration is specified through a number of "EXPECTED_" settings in the file ./integration_kit/validation/tests/IKConfig.h

The IK MCU design allows the user to instantiate either the full CORTEXM0INTEGRATION level, or a stand-alone instance of CORTEXM0.

When using the full CORTEXM0INTEGRATION level, all of the instantiation parameters are inherited from the settings in the wrapper file ./logical/models/wrappers/CORTEXM0INTEGRATIONIMP.v, where CORTEXM0INTEGRATION is instantiated.

When using only the CORTEXM0 level in the IK MCU, the parameters relevant to the CORTEXM0 level are specified in the wrapper file ./logical/models/wrappers/CORTEXM0IMP.v, where CORTEXM0 is instantiated. However, the IK MCU design allows separately instantiated Debug Access Port (DAP) and Wake-up Interrupt Controller (WIC) components to be included in the design, and these are instantiated in ./integration_kit/logical/cm0ikmcu/verilog/cm0ik_cortexm0_timing.v together with the CORTEXM0IMP. For this reason, the parameters which determine whether a debug capability is implemented (parameter DBG) and, if so, whether the debug interface protocol is JTAG or Serial Wire debug (parameter JTAGnSW), must be specified in cm0ik_cortexm0_timing.v in order to configure the DAP. Similarly, the WIC and WIC_LINES parameters are required here for the WIC instance.

However, note also that in the CORTEXM0-only configuration, the parameters DBG, WIC and WIC_LINES are required both in this wrapper file, and also in the CORTEMX0 instance itself. These parameters are not passed down through the CORTEXM0IMP instantiation, meaning that they have to be separately specified in both cm0ik_cortexm0_timing.v and CORTEXM0IMP.v, and that consistency between the two versions of each parameter is not tested by the config_check test.

The choice of integration level is controlled by a commenting or uncommenting, in the file ./integration_kit/logical/tbench/verilog/ , the line:


By default, the line is commented, resulting in instantiation of CORTEXM0 without CORTEXM0INTEGRATION in the IK MCU, and therefore the debug settings are controlled in the cm0ik_cortexm0_timing.v file as well as in the CORTEXM0IMP.v file.


The config_check.c program as delivered reports an inaccurate conclusion. If debug is expected to be included, the program tests for the expected debug protocol, and if that test is unsuccessful, it reports that debug is not present.

This incorrectly equates "expected debug protocol is not working" with "no debug is present".

    # Cortex-M0 - Config Check Test
    # JTAGnSW: No or incorrect response from DAP    -       FAIL
    # DBG: 0        (Expected 1)    -       FAIL

A more accurate test would be to tests for each possible protocol, and then compare those results with which protocol was expected.

The attached version of config_check.c can be used to replace the original version. This version implements the correction described above, and provides a more helpful diagnosis of the mismatch:

    # Cortex-M0 - Config Check Test - ARM support patch gc 1.0.0
    # A JTAG DAP responded
    # DBG  : 1      -       PASS
    # JTAG : 1      (Expected 0)    -       FAIL
    # SWD  : 0      (Expected 1)    -       FAIL



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