|ARM Technical Support Knowledge Articles|
Applies to: Cortex-M7
This Knowledge Article is primarily of interest to chip designers who have licensed the ARM Cortex-M7 processor for inclusion in their chip design.
The Cortex-M7 processor accesses its main memory system through an AMBA AXI bus interface. However, the chip designer can optionally implement some parts of the address space as local Tightly Couple Memory (TCM) and on a separate AMBA AHB-Lite bus interface.
Some editions of Cortex-M7 documentation, for example the non-confidential Technical Reference Manual (TRM), and the licensee-confidential Integration and Implementation Manual (IIM), fail to mention the specific address range occupied by the AHBP bus.
The size of the AHBP address space, and whether the AHPB bus is currently enabled, are programmed in the AHBPCR register at address 0xE000EF98.
The initialization values for these AHBPCR fields are configured by the chip designer via input signal ports CFGAHBPSZ and INITAHBPEN. The available range of sizes is zero (disabled), or 64MB, 128MB, 256MB or 512MB.
The base address of the AHBP bus is fixed at 0x40000000, the base address of the Peripheral region of the System address map, although the default memory type of device may be overridden by settings of the optional MPU.
This choice of base address aligns with the TCM base addresses; the Instruction TCM base address is 0x0, the base address of the Code region, and the Data TCM base address is 0x20000000, the base address of the SRAM region in the system address map.
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