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This article is relevant to chip designers who have licensed a Cortex-M3 or Cortex-M4 processor for inclusion in their RTL chip design, and who are using the simple combinatorial multiplexer cm3_code_mux or cm4_code_mux provided with the processor RTL to combine I-Code and D-Code master interfaces onto a single AHB-Lite bus segment.
The AMBA 3 AHB-Lite Protocol Specification requires a zero wait-state "OK" response (HREADY = 1'b1, HRESP = 1'b0) to any IDLE request.
The cm3_code_mux/cm4_code_mux is designed to consume the minimum possible gatecount.
The code mux can only accept one active address phase request at a time, so at least one of the I-Code and D-Code master interfaces on the processor must be indicating IDLE on its HTRANS output in each cycle when connected to this code mux. (The `define ARM_CODEMUX, and consequent assertion of the DNOTITRANS input, ensure that the processor observes this limitation on simultaneous accesses.)
For simplicity, the code mux returns the HREADY from the slave directly to both the I-Code and D-Code master interfaces on the processor.
If the slave produces a wait-state by de-asserting its HREADY output in response to an active request from one master interface of the processor, this means that the other (inactive) master interface of the processor will receive an invalid HREADY = 1'b0 response to its IDLE request.
The processor is designed to tolerate this invalid response.
If an AHB-Lite protocol checker IP is used in simulation, it is likely to report this occurrence as a protocol violation. Although the violation report is correct, it can be safely ignored and waived, because the processor tolerates this behavior.
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