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Applies to: GIC-400 Generic Interrupt Controller
With the GIC-400 on a Field-Programmable Gate Array (FPGA) implementation, an unexpected interrupt can be signaled to a CPU even when interrupts are not enabled in GIC distributor interrupt enable registers.
An unexpected interrupt can cause a false IRQ or FIQ exception on a CPU, and the CPU can read an interrupt ID from GICC_IAR. The interrupt ID does not have to be 1022 or 1023, and can be a normal ID.
The Register Transfer Language (RTL) code is created for Application-specific integrated circuit (ASIC). If you map this RTL code to an FPGA platform, some cells must be converted to resources that are available on FPGA. For example, the functional clock gating cells must be converted for FPGA.
Normally, the architectural clock gating cells can be bypassed only in Design For Testing (DFT). The architectural clock gating cells in the GIC-400 must be functional to ensure operation correctness. These cells must not be bypassed. If you omit them for the FPGA, it can cause unpredictable behaviors, including unexpected interrupt IDs.
Modern FPGA synthesis tools, when enabled, can recognize gated clock structures within the design and convert the logic constructs to a clock enable signal on the relevant flip flops. See the FPGA synthesis tools user guide for details.
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