ARM Technical Support Knowledge Articles

Why certain memory regions cannot be accessed in the Cortex-M3 Example System?

Applies to: Cortex-M3

Scenario

This Knowledge Article applies to chip designers who are using the Example System shipped with version r2p1 of the Cortex-M3 processor to test their Cortex-M3 based design.

If the user tries to access the 0x40000000 - 0x4000FFFF memory region without making any modification on the Example System, it results in an ERROR response on the System AHB Bus. It is possible to overcome this problem following the steps described below.

Answer

To enable access to the above mentioned 0x40000000 - 0x4000FFFF memory region a few modifications should be made on the Example System Testbench.

1) Include APB Logic

By default the Example System Testbench does not contain the APB Logic (AHB-to-APB Bridge, APB Multiplexer, 3x APB Example Slaves), therefore any access to the 0x40000000 - 0x4000FFFF memory region results in the AHB Default Slave responding with an ERROR on the System AHB Bus.

To include the APB Logic the following line should be uncommented in <Cortex-M3 folder>/example/tbench/CM3ExampleConfig.vh

//`define ARM_INCLUDE_APB

This will enable the instantiation of the AHB-to-APB Bridge, APB Multiplexer and the APB Example Slaves in the Example System Testbench.

2) Fix AHB-to-APB Bridge instantiation

There is a known issue with the Example System Testbench, that the ports in the AHB-to-APB Bridge instantiation do not match those of the module definition. To fix this issue the following lines should be modified in <Cortex-M3 folder>/example/tbench/example_tbench.v

AhbToApb 
  uAhbToApb
    (HCLK, HRESETn, HADDRS, HTRANSS[1], HWRITES, HWDATAS, HSELS_APB, HREADYS,
     PREADY, PSLVERR, PRDATA, SE, SI, HRDATAS_APB, HREADYS_APB, HRESPS_APB,
     PENABLE, PSEL, PSELS0, PSELS1, PSELS2, PSELS3, PSELS4, PSELS5, PSELS6, 
     PSELS7, PSELS8, PSELS9, PSELS10, PSELS11, PSELS12, PSELS13, PSELS14, PSELS15, 
     PADDR, PWRITE, PWDATA, SCANOUTHCLK_NC);

The module definition does not have SE, SI and SCANOUTHCLK ports, therefore the above instantiation should be modified as follows.

AhbToApb 
  uAhbToApb
    (HCLK, HRESETn, HADDRS, HTRANSS[1], HWRITES, HWDATAS, HSELS_APB, HREADYS,
     PREADY, PSLVERR, PRDATA, HRDATAS_APB, HREADYS_APB, HRESPS_APB,
     PENABLE, PSEL, PSELS0, PSELS1, PSELS2, PSELS3, PSELS4, PSELS5, PSELS6, 
     PSELS7, PSELS8, PSELS9, PSELS10, PSELS11, PSELS12, PSELS13, PSELS14, PSELS15, 
     PADDR, PWRITE, PWDATA);

3) Resolving the rest of the APB Logic using ARM's AMBA Design Kit (ADK)

This step should be only performed if the user licenses the AMBA Design Kit, otherwise it is recommended to continue with step 4) instead.

By default the Example System Testbench tries to instantiate an APB Multiplexer and three APB Example Slaves which are not part of version r2p1 of the Cortex-M3 release bundle. If the user licenses the AMBA Design Kit (ADK) the following steps should be performed.

 - copy <ADK folder>/design/global_ADK/verilog/RevAnd.v to <Cortex-M3 folder>/example/tbench/
 - copy <ADK folder>/design/EgApbSlave/verilog/rtl_source/EgApbSlave.v to <Cortex-M3 folder>/example/tbench/
 - copy <ADK folder>/design/ElementsAPB/verilog/rtl_source/MuxPToB.v to <Cortex-M3 folder>/example/tbench/

When re-building the RTL after the above steps the 0x40000000 - 0x4000FFFF memory region should be accessible without any issue, and in that case step 4) is not necessary to be performed.

4) In case the user does not license the ADK, it is recommended to use the APB Multiplexer and APB Example Slave modules from the Cortex-M System Design Kit (CMSDK). For this the following steps should be performed.

1. Copy necessary files from CMSDK

 - copy <CMSDK folder>/logical/cmsdk_apb_slave_mux/verilog/cmsdk_apb_slave_mux.v to <Cortex-M3 folder>/example/tbench/
 - copy <CMSDK folder>/logical/cmsdk_apb3_eg_slave/verilog/cmsdk_apb3_eg_slave.v to <Cortex-M3 folder>/example/tbench/
 - copy <CMSDK folder>/logical/cmsdk_apb3_eg_slave/verilog/cmsdk_apb3_eg_slave_reg.v to <Cortex-M3 folder>/example/tbench/
 - copy <CMSDK folder>/logical/cmsdk_apb3_eg_slave/verilog/cmsdk_apb3_eg_slave_interface.v to <Cortex-M3 folder>/example/tbench/

2. Commenting out instantiations of ADK modules

Since the APB Multiplexer and APB Example Slave modules in the CMSDK are slightly different from the ones in the ADK, some modification should be made on the Example System Testbench.

The following instantiations of the APB Multiplexer and APB Example Slaves should be commented out from <Cortex-M3 folder>/example/tbench/example_tbench.v, together with the PREADY and PSLVERR signal assignments.

MuxPToB uMuxPToB
  (
   // Inputs to the Mux
   PSELS0, PSELS1, PSELS2, PSELS3, PSELS4, PSELS5, PSELS6, PSELS7,
   PSELS8, PSELS9, PSELS10, PSELS11, PSELS12, PSELS13, PSELS14, PSELS15,
   PRDATAS0, PRDATAS1, PRDATAS2, 32'b0, 32'b0, 32'b0, 32'b0,
   32'b0, 32'b0, 32'b0, 32'b0, 32'b0, 32'b0, 32'b0, 32'b0, 32'b0,
   PREADYS0, PREADYS1, PREADYS2, 1'b1, 1'b1, 1'b1, 1'b1,
   1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1,
   PSLVERRS0, PSLVERRS1, PSLVERRS2, 1'b1, 1'b1, 1'b1, 1'b1,
   1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1,
   // Outputs from the Mux
   PREADY, PSLVERR, PRDATA
   );

EgApbSlave uAPB_EG0 (HCLK, HRESETn, PENABLE, PSELS0, PWRITE, PADDR[11:2], 
                     PWDATA, SE, 1'b0, SCANOUTPCLK0_NC, PRDATAS0);
  
EgApbSlave uAPB_EG1 (HCLK, HRESETn, PENABLE, PSELS1, PWRITE, PADDR[11:2], 
                     PWDATA, SE, 1'b0, SCANOUTPCLK1_NC, PRDATAS1);
  
EgApbSlave uAPB_EG2 (HCLK, HRESETn, PENABLE, PSELS2, PWRITE, PADDR[11:2], 
                     PWDATA, SE, 1'b0, SCANOUTPCLK2_NC, PRDATAS2);

assign PREADYS0 = 1'b1;
assign PREADYS1 = 1'b1;
assign PREADYS2 = 1'b1;
assign PSLVERRS0 = 1'b0;
assign PSLVERRS1 = 1'b0;
assign PSLVERRS2 = 1'b0;

3. Declaring extra testbench signals

The APB Multiplexer in the CMSDK has some extra ports compared to the one in the ADK, therefore the following signal definitions and assignments should be added to <Cortex-M3 folder>/example/tbench/example_tbench.v

`ifdef ARM_INCLUDE_APB

wire [3:0]  DECODE4BIT; // Binary encoded value of the individual PSELS inputs
wire        PSELS;      // Bitwise OR of PSELS inputs
wire [15:0] PSEL_out;   // PSEL output

assign DECODE4BIT[3] = PSELS15 | PSELS14 | PSELS13 | PSELS12 |
                       PSELS11 | PSELS10 | PSELS9  | PSELS8;

assign DECODE4BIT[2] = PSELS15 | PSELS14 | PSELS13 | PSELS12 |
                       PSELS7  | PSELS6  | PSELS5  | PSELS4;

assign DECODE4BIT[1] = PSELS15 | PSELS14 | PSELS11 | PSELS10 |
                        PSELS7 | PSELS6  | PSELS3  | PSELS2;

assign DECODE4BIT[0] = PSELS15 | PSELS13 | PSELS11 | PSELS9 |
                       PSELS7  | PSELS5  | PSELS3  | PSELS1;
    
assign PSELS = PSELS15 | PSELS14 | PSELS13 | PSELS12 | PSELS11 | PSELS10 | PSELS9 | PSELS8 |
               PSELS7  | PSELS6  | PSELS5  | PSELS4  | PSELS3  | PSELS2  | PSELS1 | PSELS0;

`endif

4. Instantiating APB Multiplexer and APB Example Slaves

With the above signals the APB Multiplexer and APB Example Slaves can now be instantiated in the Example System Testbench by adding the following lines to <Cortex-M3 folder>/example/tbench/example_tbench.v

`ifdef ARM_INCLUDE_APB

cmsdk_apb_slave_mux #(1,1,1,0,0,0,0,0,0,0,0,0,0,0,0,0) uMuxPToB
  (DECODE4BIT, PSELS,
   PSEL_out[0],  PREADYS0, PRDATAS0, PSLVERRS0,
   PSEL_out[1],  PREADYS1, PRDATAS1, PSLVERRS1,
   PSEL_out[2],  PREADYS2, PRDATAS2, PSLVERRS2,
   PSEL_out[3],  1'b1,     32'b0,    1'b1,
   PSEL_out[4],  1'b1,     32'b0,    1'b1,
   PSEL_out[5],  1'b1,     32'b0,    1'b1,
   PSEL_out[6],  1'b1,     32'b0,    1'b1,
   PSEL_out[7],  1'b1,     32'b0,    1'b1,
   PSEL_out[8],  1'b1,     32'b0,    1'b1,
   PSEL_out[9],  1'b1,     32'b0,    1'b1,
   PSEL_out[10], 1'b1,     32'b0,    1'b1,
   PSEL_out[11], 1'b1,     32'b0,    1'b1,
   PSEL_out[12], 1'b1,     32'b0,    1'b1,
   PSEL_out[13], 1'b1,     32'b0,    1'b1,
   PSEL_out[14], 1'b1,     32'b0,    1'b1,
   PSEL_out[15], 1'b1,     32'b0,    1'b1,
   PREADY, PRDATA, PSLVERR);
cmsdk_apb3_eg_slave #(12) uAPB_EG0 (HCLK, HRESETn, PSELS0, PADDR[11:0], PENABLE, PWRITE, PWDATA, 
                                    4'b0, PRDATAS0, PREADYS0, PSLVERRS0);
  
cmsdk_apb3_eg_slave #(12) uAPB_EG1 (HCLK, HRESETn, PSELS1, PADDR[11:0], PENABLE, PWRITE, PWDATA, 
                                    4'b0, PRDATAS1, PREADYS1, PSLVERRS1);
  
cmsdk_apb3_eg_slave #(12) uAPB_EG2 (HCLK, HRESETn, PSELS2, PADDR[11:0], PENABLE, PWRITE, PWDATA, 
                                     4'b0, PRDATAS2, PREADYS2, PSLVERRS2);

`endif

When re-building the RTL after the above steps the 0x40000000 - 0x4000FFFF memory region should be accessible without any issue.

Rate this article

[Bad]
|
|
[Good]
Disagree? Move your mouse over the bar and click

Did you find this article helpful? Yes No

How can we improve this article?

Link to this article
Copyright © 2011 ARM Limited. All rights reserved. External (Open), Non-Confidential