ARM Technical Support Knowledge Articles

Why certain memory addresses are being accessed multiple times when using Load Multiple or Store Multiple instructions?

Applies to: Cortex-M3, Cortex-M4, Cortex-M7


This Knowledge Article applies to software developers writing code to processors implementing the ARMv7-M architecture, such as Cortex-M3, Cortex-M4 or Cortex-M7.

The user might observe that if a Load Multiple or Store Multiple instruction gets interrupted, in certain cases after returning from the interrupt the processor loads or stores memory addresses that have been already loaded or stored before taking the interrupt.

In case of accessing a Device or Strongly-ordered memory region, this is undesirable and potentially causes erroneous behaviour.


To improve interrupt response and increase processing throughput, the ARMv7-M architecture allows the processor to take an interrupt during the execution of a Load Multiple or Store Multiple instruction, and can either continue or restart the execution of the instruction after returning from the interrupt. The behaviour detailed in the Scenario can occur in certain cases when the Load Multiple or Store Multiple instruction continued after an interrupt, and occurs each time if the Load Multiple or Store Multiple instruction gets restarted.

During the interrupt processing, the Execution Program Status Register's ICI/IT bits hold the continuation state, which makes the processor able to continue the Load Multiple or Store Multiple instruction from the point when it was interrupted. However, the following limitations apply:


To avoid the above explained error-prone behaviour, the following rules should be held when accessing Device or Strongly-ordered memory with Load Multiple or Store Multiple instruction:

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