ARM Technical Support Knowledge Articles

What happens when the EDBGRQ signal is asserted?

Applies to: Cortex-M3

Answer

This will either put the core into debug state, take the Debug Monitor exception or it will be ignored if both halt and monitor are disabled. The 'C_DEBUGEN' bit in the Debug Halting Control and Status Register needs to be set to enable halt mode. The Debug Monitor is classified as a fault and can only occur if halting debug is disabled (C_DEBUGEN is low) and the debug monitor is enabled (MON_EN bit is set in the Debug Exception and Monitor Control Register).

If an exception occurs while the core is in halt debug state it is pended, i.e. it will be taken when the core returns from debug state. If the core is processing a debug monitor exception and a new exception occurs, which is higher priority than the current exception then it pre-empts it, otherwise it is pended.

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