ARM Technical Support Knowledge Articles

What are STCALIB and STCLKEN or STCLK, and how should I connect them in the SoC?

Applies to: Cortex-M0, Cortex-M0Plus, Cortex-M3, Cortex-M4

Answer

The STCALIB and STCLKEN / STCLK inputs relate to the provision of a SYSTICK (System Tick) capability - in effect, a resource to allow SoC-indepenent program code to measure real time - in the ARM v6-M and v7-M Architecture. The capability is described in section B3.3 of the ARM v6-M Architecture Reference Manual and ARM v7-M Architecture Reference Manual.

The SYSTICK counter in Cortex-M core is clocked by the free-running clock (eg. SCLK, FCLK), and it can count either the free-running clock itself, or it can count the cycles of an independent timing reference signal STCLKEN or STCLK (typically at a much lower frequency) if one has been provided on the SoC.

To indicate which timing reference has been provided on the SoC, and the exact properties of that reference, the designer must supply reference information (usually statically tied off) on the STCALIB inputs. These configuration values can be read by code running on the processor as bit fields in the SysTick Calibration Value Register (SYST_CALIB). NOREF=STCALIB[25], SKEW=STCALIB[24], TENMS=STCALIB[23:0].

If the timing reference signal is supplied, NOREF should be tied LOW, and the other fields should be programmed according to the properties of the timing reference. If no timing reference signal is supplied (STCLKEN / STCLK is tied off), NOREF should be tied HIGH and the other fields should be programmed according to the properties of SCLK / FCLK, and making sure to remember that this clock may be designed to run at reduced rate during SLEEP mode, which would affect its usefulness as a real-time clock reference. Note also that if a constant frequency timing reference is used, then it is necessary that the SCLK / FCLK frequency (even if reduced during SLEEP mode) must never extend to a period close to a full pulse width of the timing reference (HIGH or LOW pulse) otherwise the cycle counting may miss a cycle and consequently timing accuracy may be lost. However, as long as this requirement is met - ie. F(clock) >= 2.5 * F(timing reference), roughly speaking - then the full accuracy of the SYSTICK function can be retained even while the processor is asleep and the SCLK / FCLK is running at reduced rate to conserve power.

If a constant frequency reference signal is supplied (STCLKEN / STCLK, or SCLK / FCLK if no STCLKEN / STCLK is supplied), the TENMS value of STCALIB[23:0] should indicate how many cycles of the reference will be equal to 10ms of real time. If that number does not divide exactly as an integer value, then the SKEW field should be set, to indicate that there is a systematic error (drift) in the timing, implying that it should not be used for implementing a real-time clock.

If the timing reference signal (STCLKEN / STCLK, or SCLK / FCLK if no STCLKEN / STCLK is supplied) is driven with a variable frequency, the TENMS value of STCALIB[23:0] should be zero.

If STCLKEN / STCLK is tied off, NOREF should be set. This implies that SCLK / FCLK is the only available source of reference timing.

A software application can read the TENMS value and the SKEW and NOREF fields to discover what kind of time-measuring resources have been supplied by the chip designer. It can then calculate the number of reference clock cycles required for any arbitrary time period, by scaling from the TENMS value, and use the calculated period to program the timer reset value to generate regular SYSTICK events at this chosen frequency.

In fact, TENMS is defined to be the 10ms reload value of the SYSTICK counter, which is a downcounter from (n-1) to 0; therefore the TENMS value needs to be one count less than the actual number of cycles required for 10ms. This means that the TENMS value can be loaded directly into the SysTick Reload Value Register (SYST_RVR) to obtain a 10ms interval, but software which wishes to scale the counter reload value to obtain a time period other than 10ms should first read the TENMS value, then add 1 to give the true number of cycles required for 10ms, then scale this value to the desired cycle count, then subtract 1 to get the new counter reload value.

For example:

If STCLKEN / STCLK is constant 1MHz, then the TENMS value should be set to 10000 - 1 = 9999. This results is an exact integer with no rounding, so there is no additional error introduced by the SysTick logic - therefore this reference clock would be suitable for use in a real-time clock (ie. it would be as accurate as the original 1MHz clock source) and the SKEW field should be set to ZERO, and the NOREF field should be set to zero as the STCLKEN / STCLK is provided.

An application could make use of these numbers like this:

Rate this article

[Bad]
|
|
[Good]
Disagree? Move your mouse over the bar and click

Did you find this article helpful? Yes No

How can we improve this article?

Link to this article
Copyright © 2011 ARM Limited. All rights reserved. External (Open), Non-Confidential