ARM Technical Support Knowledge Articles

General: Can a master change the address/control signals during a waited transfer?

Applies to: AHB

Answer

Yes. If the address/control signals are indicating an IDLE transfer then the master can change to a real transfer (NONSEQ) when HREADY is low.

However, if a master is indicating a real transfer (NONSEQ or SEQ) then it cannot cancel this during a waited transfer unless it receives a SPLIT, RETRY or ERROR response.

See also:

Article last edited on: 2014-02-06 14:58:08

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