General: Is it legal for a master to change HADDR when a transfer is extended?

If a master is indicating that it wants to do a NONSEQ or SEQ transfer then it cannot change the address during an extended transfer (when HREADY is low) unless it receives an ERROR, RETRY or SPLIT response.

If the master is indicating that it wants to do an IDLE transfer then it may change the address, but if it is indicating a BUSY transfer it can only change the address if the current undefined length burst is being terminated (with HTRANS also changing to IDLE or NONSEQ).

See also:

• AMBA 2.0 Specification
• Can a master change the address/control signals during a waited transfer?
• Can HTRANS change whilst HREADY is low?
• What default state should be used for the HREADY and HRESP outputs from a slave?