ARM Technical Support Knowledge Articles

Section 2.2. MMCI Clocks

Applies to: PL181 Multimedia Card Interface V2


Documentation (Integration manual page 9) states that the following conditions must satisfied:

PCLK faster than MCLK

PCLK slower than MCLK

Which one should it be?

There are two clock sources for the MMCI: PCLK and MCLK and there are two possible clocking configurations.

One is where both clock sources are from the AMBA system clock (APB - PCLK). Note here though, that the card clock, MMCICLKOUT, is generated using the MCLK as a reference.

The other is where PCLK and MCLK are clocked from separate sources. It is in this configuration, when the clocks are free running, that the above conditions must be satisfied.

What is FBCLK and are there any constraints on FBCLK?

FBCLK is used to delay outputs in respect to MCICLK.

There is only one requirement on the FBCLK and that is that, the delay from the MMCICLK (external pad) to FBCLK must be long enough to meet the card input's hold time. This should be met on the card and not on the ASIC/chip outputs, because different loads (PCB wires, connector, card load...) might unevenly increase pad output delays.

A rule of thumb is that, the delay (MMCICLK>FBCLK) should be greater than the maximum card hold time plus the safe margin. Where the safe margin is the difference of pad delay for maximum and zero load. It should also not violate setup time. If it is delayed too much, then the MMCI outputs are driven too late and the card setup time is violated.

We recommend that the MMCI feedback clock be driven from the MMCICLK pad, because this is the easiest and safest way to do it. This method is eaisier since you are strarting from the external clock and all that is needed to be done is to add hold time plus margin.

See Timing Diagrams in the Technical Reference Manual for more details on page 2-24.


MMCICLK delay: MCLK to the MMCICLK pad

FBCLK delay: MCLK to the unused pad plus unused pad to the MMCI output registers (via clock tree) plus register to pads


Clock period - setup time > FBCLK_delay - MMCICLK_delay > hold time + margin.

How was the output/feedback clock handled in verification of the PL181?

The MMCI was tested on an integrator board (FPGA). The MMCICLK pad was connected to another pad on the FPGA externally (via a wire on the PCB). This was the easiest way to gaurantee clock delay (MMCICLK>FBCLK) each time the MMCI was synthesised and placed and routed.

Figure 2-15 on page 2-24 of the MMCI Technical Reference Manual shows the MMCICMD and MMCIDAT timings. Referring to the MMC specification in chapter. 6.7 on page.78, the input setup and hold time is specified as 3 ns. What are these times related to? MMCICLK or MMCIFBCLK?

You need to delay the outputs enough to meet the hold time, but not too much to violate setup time of a card(s) used in the current system.

In order to account for on-chip and off-chip delays between the MMCICLKOUT output and the MMCICLKOUT seen at the card input, a re-synchronisation mechanism is required in the MMCI. All resynchronisation is done by clocking all the MultiMediaCard related input/output signals with the rising edge of MMCIFBCLK,the fedback clock. The command, data and other output lines of the MMCI are driven with respect to MMCIFBCLK and not MMCIBCLK.

The resynchronisation logic within the MMCI,using the fedback clock, MMCIFBCLK, enables the controller to meet the 3ns hold requirements on all outputs.

There are 2 cases, input and output signals.

Card inputs (MMCI->card):

Timing is in respect with the external MMCI clock (this is the MMCICLKOUT driven through the output buffer and pad). We can delay the FBCLK in respect to the MCLK to meet the timing on the card. By increasing the delay, we are delaying the MMCI output signals (external) in respect to the external MMCI clock to meet the hold time. However if the delay is increased too much, then the setup time might be violated.

Card outputs (card->MMCI):

Card outputs are driven in respect to the external MMCI clock, and sampled internally on the FBCLK. We can change FBCLK delay and/or add delay on the signal pad to the MMCI register path.

Article last edited on: 2008-09-09 15:47:25

Rate this article

Disagree? Move your mouse over the bar and click

Did you find this article helpful? Yes No

How can we improve this article?

Link to this article
Copyright © 2011 ARM Limited. All rights reserved. External (Open), Non-Confidential