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Section 2.3. FIFOs

Applies to: PL181 Multimedia Card Interface V2


The Technical Reference Manual refers to the Data FIFO, the Transmit FIFO and the Receive FIFO. What is the relationship between these FIFOs?

The MMCI consists of one FIFO, the Data FIFO, which can be either disabled, transmit enabled or receive enabled, depending on the value of the TxActive and RxActive signals. The Tx/RxActive signals are mutually exclusive. This FIFO contains a 32-bit wide, 16-word deep buffer and transmit and receive logic. Now the Transmit FIFO refers to the transmit logic and data buffer when TxActive is asserted and the Receive FIFO refers to the receive logic and data buffer when RxActive is asserted.

Could you please explain what the MMCIFifoCnt register is supposed to be counting and what its purpose is?

The MMCIFIFOCNT register contains the remaining number of words to be written to or read from the FIFO. The data length register is used to load the FIFO counter (when the Enable bit is set in the data control register).

The functionality of the MMCIFifoCnt register is distinctly different from the data counter. The data counter offers a 'card-view' of the data transfer, and the MMCIFifoCnt register a 'FIFO view'.

The data counter counts the bytes transfered to the card as they are written out to the card by the MMCI state machine. The MMCIFifoCnt register counts the words remaining to be written to the FIFO(s). Since the two will typically be out of phase, they reflect very different data.

Please Note that the data count register should be read *ONLY* when the transfer finishes, otherwise it might contain an unpredictable value.

For reads, the Fifo Count Register could be used to drain the FIFO. When the receive transfer finishes, the FIFO counter will hold the number of words in the FIFO. The MMCI driver can use this value to drain the FIFO after the receive transfer has finished.

Note that the fifo count register use is optional, a driver can be written without referencing the data counter or the FIFO counter.

Since data transfer is never initiated by the card, but is driven by the driver, state can be 'cached' at the driver which can maintain its own counters. FIFO draining is then performed using the flags (while not FIFOempty...).

The FIFO counter is available for alternative strategies.

Article last edited on: 2008-09-09 15:47:25

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