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Section 2.1. Single Versus Dual AHB Master Interface

Applies to: PL08x DMAC (DM & SM)


There are two AHB master interfaces, why are there two? Can we have just one of these master interfaces?

The two master interface allows, for example, the PrimeCell DMA controller to transfer data directly from the memory connected to AHB port 1 to any peripheral connected to AHB port 2. This can take place whilst a transfer is taking place on AHB port 1 independent of what is taking place on AHB port 2. The dual master interface minimizes system bus overhead performance.

There is a single master DMA controller in the form of PL081, whereas the PL080 has a dual master interface.

What types of bus accesses take place during data transfer between the DMA and FIFO at the peripheral for the single and dual master DMA controllers?

PL081 - Single Master
For DMA to peripheral transfers, INCR16 will be used for byte accesses and INCR4 for word accesses. Similarly, for peripheral to memory. Latency is higher in single master DMA as source and destination are on the same AHB bus/port with transfers taking place from source to FIFO to destination.

PL080 - Dual Master
The latency will be reduced here the source and destination can be on separate buses, hence data can be written out in the next cycle. If the memory is the source, again INCR16 will be used for byte accesses and INCR4 for word accesses, but you are limited by the size of the FIFO. If the memory is the destination then INCR will be used.

Combinations of transfers across the Dual Master Interface

Is the AHB master interface capable of routing data between two devices over the same interface or must they cross over to the other master interface?

You can have all combinations of transactions as follows:

  • AHB1 to AHB2
  • AHB2 to AHB1
  • AHB1 to AHB1
  • AHB2 to AHB2

You can also have transactions from source to destination on the SAME AHB port. The data would need to be read from the AHB port to the DMA controller (AHB read). The data would then need to be transferred from the DMA controller to the AHB port (AHB write).

Crossing over to the other port is a more efficient methodology as data can be read from AHB port 1 (AHB read) for example, and at the same time data can be transferred to the other AHB port 2 (AHB write).

Sequence for Transferring data across the AHB ports:

  1. Read in one 4 32-bit word burst into the channel FIFO via AHB port1
  2. As soon as the data is registered inside the FIFO, and AHB port2 is granted, then the data is drained to the destination via AHB port2. Number of beats attempted in this transfer depends on the destination width,burst size, amount of data available in the FIFO when the master started of.
  3. Source fetch via AHB port1 can continue if source request is availabe, AHB port 1 is granted and sufficient space is available in the FIFO.
  4. We can see both source fetch and destination drain happening at the same time.

What happens in the case where channel 1 is a DMA transfer from a slow source on AHB 1 to a destination on AHB 2 and channel 2 is a DMA transfer from a source on AHB 2 to a destination on AHB 2? Will AHB2 be stalled?

If a request goes active on channel 1 and the channel is waiting for data from the source, on AHB 1. AHB 2 will not be tied up. AHB 2 will only be requested and used by channel 1 when required. This means that if Channel 2 goes active while Channel 1 is waiting for data, Channel 2' request can go ahead.

Article last edited on: 2008-09-09 15:47:25

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