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Applies to: PL08x DMAC (DM & SM)
What is the difference between width a transfer and the burst size?
The width of a transfer is fixed, so if it is, say 8, then 8 bits will be read and 8 bits will be written and the DMA controller cannot change that.
The burst size, on the other hand, is programmable and tells the DMA controller how much data there is to be transferred when the burst request signal goes active.
Will the DMA carry out byte-sized bursts if the width is defined as byte wide, and INCR type bursts if burst length is defined as 4,8 etc?
Yes, if the Source/destination width is defined as byte-wide the DMAC will carry out byte-sized transfers, and if the width is defined as 16,32 the DMAC will carry out half-word, word transfers. If burst length is defined as 4,8 etc. these will be INCR, INCR4, INCR8 etc.
For example, if the width is 8-bits and a DMACSINGLE request is made, then the DMA will carry out a single transfer of 8-bits.
If the width is say 16- bits and source burst size is 256, and the DMACBURST request (and perhaps DMACSINGLE request) is used, then the DMAC will carry out 256 8-bit transfers.
AHB HBURST information is provided to AHB peripherals to ensure that transfers are carried out as efficiently as possible and various combinations of SINGLE, or rather INCR (as the DMAC treats an AHB SINGLE as an INCR), INCR4, INCR8 will be used as necessary to transfer the required data.
Is it possible to do byte accesses to 32-bit wide RAM, if at the end of a DMA transfer there is an odd number of bytes left?
The DMA controller contains packing hardware logic for channel FIFO write-data and unpacking logic for channel FIFO read-data. If there are narrow source data accesses, the data needs to be 'packed' into the FIFO for optimal use. Similarly, for narrow destination accesses, only a portion of a FIFO words to be extracted, 'unpacked. But the DMA controller cannot change the fact that the source transfer was, say 8 bits and the destination is word; it will carry out a byte read from the source and a byte write to the destination peripheral unless it is programmed using an LLI.
How does the packing/unpacking logic work in the DMAC?
This packing/unpacking logic is for the case where there are narrower source transfers or narrower destination transfers.
Thus for narrow source transfers, the data needs to be 'packed' into the FIFO for optimal transfer and likewise for narrow destination transfers, only a portion of the data in the FIFO is required and so extracted or 'unpacked'.
If data being written to the FIFO is narrower than a word, then it is required that data is written into specific byte-lane (s), without destroying the contents of the remaining bytes. This is achieved by using the FifoWrMask and FifoWrData signals.
For writing to a destination which is narrower than a word then, there is a RdSubPtr signal which is used to drive the FIFO read data based on the RdSubPtr.
How can INCR types of transfers be avoided?
In this case, the DMASINGLE request signal can be used to transfer data, but this signal will have to be asserted every time data is required to be transferred, until the full amount has been transferred. When this signal is asserted the amount of data transferred will be based on the defined source/destination width.
Article last edited on: 2008-09-09 15:47:25
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