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Applies to: PL08x DMAC (DM & SM)
What size transfers does the DMAC support?
The PrimeCell DMAC supports 8- (byte), 16- (halfword) and 32- (word) bit transfers on the AHB.
Does the burst size defined for each channel influence the type of AHB transfer that is carried out? If not, how do I define that a channel should carry out burst transfers?
There are two types of DMA request signal: DMACxBREQ and DMACxSREQx.
The DMACxBREQ signal causes a programmed burst number of words to be transferred whereas the DMACxSREQx causes a single word to be transferred.
The size of the AHB transfer depends on a number of factors:
Depending on the factors mentioned above, the DMA controller will use INCR/INCR4/INCR8/INCR16. The DMA controller will use the largest burst size it can. INCR is used for the smallest transfers - single, double and triple data transfers. After that it may be a combination of INCR4 and INCR or INCR8 and INCR4 and INCR depending on the number of transfers. If the number of transfers does not fit into the standard AHB burst types then INCR will be used.
What DMAC request signals should be used for bursts of one transfer?
The DMA controller has two sets of request signals that can be used by peripherals to request a data transfer. If a peripheral does not have burst capability or it is not able to use the burst or last request signals, this will mean that the DMA controller will have to be the flow controller. If a peripheral only transfers single words of data, thus only using the DMASREQ signal; then it is not necessary to connect the burst request signal; although you may choose to do so.
Page 2-12 of the Technical Reference Manual shows examples of the DMA request and response connectivity. As the peripheral you mention will not make full use of all the signals, output signals that are not required are left unconnected, whilst input signals that are not required must be tied LOW (in this case DMACxBREQ, DMACxLSREQ and DMACxLBREQ must be tied LOW).
So you may have something like this:
So in this situation the peripheral will assert the DMASREQ signal and then the DMA controller will use the DMACCLR signal to clear of acknowledge the request. Appendix B in the Technical Reference Manual shows different scenarios when using the DMA controller and peripherals or memory.
Section B.4.2 for example shows a memory-to-peripheral example with the second diagram (Figure B-2) showing that if you have transactions comprising of single requests, you can use the burst request signal DMACBREQ, and set the burst size to 1.
So in summary,either DMASEQ or DMABREQ (where burst set to 1) can be used.
Could I use DMASREQ connected to DMACBREQ (where burst size is set to 1)?
Yes. Either DMASREQ (peripheral) can be connected to DMACSREQ (DMAC) or DMASREQ (peripheral) can be connected to DMACBREQ (DMAC) and burst size set to 1. In the latter case, with DMASREQ connected to DMACBREQ, the DMAC will treat it as a single request due to the fact that the burst size is set to 1. Both configurations should produce the same result.
Cases where requests from peripherals (be it source/destination) are ignored are:
For source requests:
Memory DMAC/Dest All the source requests are ignored.
Peripheral DMAC/Dest Source LB and LS requests are ignored.
For destination requests:
Memory DMAC/Source All the destination requests are ignored.
Peripheral DMAC/Source The dest single requests and
LB-requests are ignored.
Section 3.5 on page 3-34 of the Technical Reference Manual states that 'Bursts do not cross the 1KB address boundary'. Does this refer to the address at the destination? How does the DMAC continue the rest of the burst?
If a burst crosses a boundary, HBURST goes to 001 (Burst of unspecified length) for smaller than quad transfers filling (emptying) up one 1KB space and then the remainder over to the next before resuming quad bursts (011). HBURST also goes to 001 if the FIFO in the DMAC is full and must be emptied to the destination slowly (ie data streaming to the destination word by word). Or, the FIFO is filled from a source lacking enough data for a quad burst.
How does the DMAC behave while HBURST=001 once the 1KB boundary has been crossed, for, for example, a peripheral which always provides data in 4 words with the quad burst in mind?
The DMA controller will be programmed to perform a burst of 4. When the peripheral requests a transfer by asserting the DMACxBREQ signal the DMA controller will read 4 words from the peripheral. The peripheral provides a data word for each memory access.
AHB bursts are allowed to be broken. This is performed by the AHB arbiter granting a higher priority master the bus. Whether this kind of burst breaking occurs or not depends upon the design of the AHB arbiter and the system design.
This burst breaking is indicated to the slave peripheral by the HTRANS signal going to NONSEQ. Therefore to be fully AHB compliant the peripheral should be able to handle this.
How does the DMAC deal with alignment?
The source and destination address must be aligned to the source and destination widths.
Article last edited on: 2008-09-09 15:47:25
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