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Applies to: PL08x DMAC (DM & SM)
Can the DMAC be programmed such that we can ensure four-word-bursts or four-single-word bursts (ie no bursts of 3 words)?
No there is no way that the DMAC can be programmed to do this. If, say, the source/destination width is a word and the burst size is set to 4, then most of the time HBURST will be INCR4, but the DMAC cannot be 'forced' to do this.
Is there a way to ensure that all four words have been transferred to the memory before the DMAC request is granted? If, for example, there are 4 words to be transferred from a peripheral to a memory and only 3 are transferred, hence there is still one word in the FIFO. Then, another peripheral makes a DMA request; is there a way to ensure that all four words from the previous request have been transferred before the next DMAC request is granted?
No, there is no way of ensuring this. The only possible way round this is, if the peripheral in some way could use the DMACCLR signal from the destination peripheral but that is just an idea.
Can the FIFO size of the DMAC be controlled to gaurantee only four-word-burst?
No, as the size of the FIFOs is fixed, each channel has a 4 would FIFO.
If the DMAC is the flow controller and the transfer count is an uneven number of bytes, will the destination transfers be automatically byte-wide transfers?
The destination transfers will not automatically be byte transfers, they actually have to be programmed into the DMAC. It is recommended that since the transfer count is an odd number of bytes, that the destination should be programmed to be byte-wide as programming it to anything other than the byte-wide (ie halfword or word) would cause data to be lost.
Article last edited on: 2008-09-09 15:47:25
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