|ARM Technical Support Knowledge Articles|
Applies to: PL08x DMAC (DM & SM)
What endian configuration does the DMAC support and does it affect the DMAC transactions?
The DMA controller supports both little and big endian configurations. It defaults to little on reset. The endianness of each AHB master can be set individually as the AHB masters need not have the same endianness.
All transactions on the AHB slave programming bus of the DMAC are and must be 32-bits wide. This eliminates endian issues when programming the DMA controller.
All transfers to and from it must be 32-bit. This means that even 8-bit, 16-bit, 19-bit registers should and can only be accessed with 32-bit transfers.
Article last edited on: 2008-09-09 15:47:25
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