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Applies to: PL08x DMAC (DM & SM)
This section looks at various scenarios in the way of configurations with possible problems and solutions and the way the DMAC handles these configurations.
DMAC source is a byte-wide peripheral, which carries out single transfers.
DMAC destination is a 32-bit wide memory that carries out burst transfers
CASE 1: Number of bytes read from the source is not a multiple of 4
The number of bytes should always be a multiple of 4.
Destination bus width = 8 bit
Burst size = 16 bytes
Transfer count = 15 bytes
How the DMAC handles this scenario depends whether the source and destination are on the same AHB bus or not.
If they are on the same AHB bus then the typical sequence will be:
Source to Destination:
If they are on different AHB buses then how the DMAC handles it will depend on a number of factors that have been mentioned before:
The DMAC will build/break up the transfers appropriately based on the information programmed into the DMAC.
We have a peripheral that has a byte-wide receive register but is on a 32-bit bus. How does the DMAC handle this situation?
Ideally, you should ensure that you use peripherals whose natural word size is 32 to take full advantage of the 32-bit bus used by the DMAC.
However, if you do have a peripheral whose natural word size is not 32 and it is only receiving data, then the DMAC duplicates this data internally.
Scenarios on Transfer Types
Peripheral-to-Memory Receive Transfers with Peripheral as Flow Controller
If the source of a DMA is in memory and the destination is a peripheral, then will the DMAC get data from the memory before the peripheral requests it?
No, the DMAC will only get data from memory when the peripheral requests the data.
If a DMAC gets an error from a source access, will it stop the destination access for this channel, or will it empty its FIFO before stopping?
If an error is flagged during a DMA transfer by a peripheral, the DMA controller automatically disables the DMA stream and any data in the FIFO will be lost. For an error to occur (this will be signalled on the HRESP signal) there would have to be something majorly wrong. The channel will be disabled and the DMA controller will generate an interrupt to your interrupt controller.
If there are a number of bytes left in the DMAC FIFO which do not match the width of the destination, what happens if there is a problem and the DMAC is halted?
The channel will be disabled any data left in the FIFO will be lost. There are ways of disabling a channel without data being lost; this is described on page 3-4 of the Technical Reference Manual in section 3.2.4.
If the transfer count in scenarios A and B is odd, how does the DMAC access the data?
The best way for these scenarios would be to define the destination width as byte-wide and the burst transfer as high as possible, say 8 or 16, to allow more data to be built up in the DMAC's FIFO before it is passed on to the destination. This will help prevent any loss of data.
In scenarios A and B, the destination bus width is configured to 8 bits and the burst size is 16 bytes and the transfer count is set up to be 15 bytes. The DMAC collects 15 bytes inside its internal FIFO and then writes 15 bytes to the memory in a manner depending on whether the source and destination are on the same or different AHB ports.
Article last edited on: 2008-09-09 15:47:25
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