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Section 2.18. Setting Up The DMAC For A Transfer

Applies to: PL08x DMAC (DM & SM)


What are the steps required for setting up a DMA transfer?

There are three steps to performing a DMA transfer:

1) Configuring and enabling the DMAC;
2) Setting up the linked lists if required;

3) Programming and enabling the suitable DMA channel.

Step 1) involves the following:
Writing to the DMACConfiguration register :

Bit 2 = 0 Master 2 little endian
Bit 1 = 0 Master 1 little endian
Bit 0 = 1 DMAC enabled

Step 2) May or may not be relevant
It will not be relevant if a single transfer is being carried out in which case DMACxlli should be programmed to zero.

However if a linked list is required, steps required are:

  • setting up the linked list in memory;
  • copying the LLI into the DMAC channel registers including writing the:
  • DMACCxSrcAddress
  • DMACCxDestAddress
  • DMACCxLLI and
  • DMACCxControl

Step 3) Involves:
(i) Choosing a free DMA channel with the priority needed, with DMA channel zero having the highest priority and DMA channel 7 the lowest.

NOTE : for memory-to-memory transfers, you must program these transfers with a low priority channel (6 or 7) otherwise the other DMA channels cannot access the bus until the memory-to-memory transfers have finished or other AHB masters cannot perform any transactions.

To find out if there are any channels enabled, when trying to choose a free channel, read the DMACEnbldChns register.

(ii) Clearing any pending interrupts by writing to the DMACIntCClr and DMACIntErrClr regsiters; as the previous channel operation may have left interrupts active.

(iii) and (iv) Writing the source and destination addresses in the DMACCxSrcAddr and DMACCxDestAddr registers respectively.

(v) Writing the next LLI in to the DMACCxLLI or write 0 into this register for single packet transfers.

(vi) Writing the control information in the DMACCxControl register

(vii) Then finally writing the configuration information in the DMACCxConfiguration register and if the the Enable bit is set then the DMA channel is automatically enabled.

Key things here for memory-to-memory transfers are:

bits 13:11 - flow control and transfer type is the PrimeCell DMAC and memory-to-memory transfer and should be 000
bits 9:6 and 4:1 do not matter for memory transfers

bit 0 - enable DMA channel =1

For memory-to-memory transfers, software programs the DMA channel and once it is enabled the DMA channel commences the transfer without DMA requests and will stop when either the data has been transferred or the channel has been disabled by software.

There is no need to set the DMACSBREQ as data should be transferred automatically when the DMAC is enabled.

It is generally recommended that software and hardware requests should not be used at the same time.

Article last edited on: 2008-09-09 15:47:25

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