ARM Technical Support Knowledge Articles

Fatal Error: The processor failed to re-enter debug state after a system speed access

Applies to: Multi-ICE


Multi-ICE normally makes the core access memory at system speed when displaying or modifying the contents of a memory window, or when loading an image to memory.

During a system speed memory access the core exits debug state, and after the access it needs to go back into debug state. If a timeout occurs in Multi-ICE before the core is back into debug state, it reports this error message.

This is normally caused by the following reasons:

  • The core is reset during the system speed access
  • The core clock is stopped
  • The core is stalled by the memory system: BWAIT is high or HREADY/nWAIT is low
  • The core clock is much slower than TCK
  • The JTAG signals, especially TCK, are not of sufficient quality

A special case in which this can happen, is if an exception occurs (e.g. data abort), but there is no memory at the vector location, which then also causes an abort, resulting in an infinite abort loop.

Article last edited on: 2008-09-09 15:47:29

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