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Applies to: Multi-ICE
The maximum TCK frequency that can be generated with Multi-ICE is 10MHz. However, the actual maximum TCK frequency that you can use to debug a target depends on the target itself.
According to the JTAG standard, TMS, TDI and TDO are driven on the falling edge of TCK and are sampled on the rising edge of TCK. The maximum TCK frequency is limited by the delays on the JTAG signals and the setup time requirements of both Multi-ICE and the target.
Multi-ICE timing characteristics are available in Appendix F.2 of the Multi-ICE v2.2 User Guide.
For example, ARM7TDMI. The maximum TCK speed depends only on the silicon process and the delays on the JTAG signals. You should normally be able to work with TCK faster than 1MHz.
For example, ARM926EJ-S.
Synthesizable cores must implement the JTAG synchronisation logic, which samples the JTAG signals with the core clock.
The three sampling flip-flops set the theoretical maximum TCK frequency, which is one sixth of the core clock frequency (one eighth in ARM11) - See the How does adaptive clocking work? FAQ entry for more information.
The real maximum TCK frequency will be lower than this and will depend on the core clock frequency, the delays on the JTAG signals and the setup time of Multi-ICE and the ASIC.
In practice, you need to experiment to find out the maximum possible TCK frequency. When beginning to work with a new design you should set a low TCK frequency. You can determine the maximum frequency for reliable operation by experimentation.
If your target provides RTCK, you can also configure Multi-ICE in adaptive clocking mode. Multi-ICE will automatically work at a TCK frequency close to the maximum possible one.
Article last edited on: 2008-09-09 15:47:30
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