|ARM Technical Support Knowledge Articles|
For RVI, RVI-ME and Multi-ICE, vector_catch is a mechanism used to trap processor exceptions. This feature is typically used in the early stages of development to trap processor exceptions before the appropriate handlers are installed. The vectors to trap may be selected by editing the vector_catch value.
With RVI & RVI-ME
The vector_catch value can be configured via the RVD GUI in the Processor Events window. To access this, from the RVD main menu select: Debug, Simple Breakpoints, Processor Events.
Individual vector_catch settings can also be configured via the RVD CLI using, (for example):
The value of vector_catch may be overridden for a single debug session from the Debugger Internals tab of the Register Window (see Where do I find Debugger Internal Variables in RVD?). The value of vector_catch represents a bit field, where a set bit corresponds to a trapped exception - the lsb corresponds to the reset vector. Although the value can only be displayed in hexadecimal, values may be entered in binary format using the notation 0b. The default value of 0x13B (0b100111011) corresponds to trapping:
|SWI||No||SWI vector may also be trapped by the debugger to enable standard semihosting|
|Reserved (Address)||No||This vector is not used on current ARM cores, there is no need to trap this|
|Error||Yes||This a deprecated feature and performs no function|
Article last edited on: 2008-09-09 15:47:31
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