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Applies to: ARM7TDMI
There are several ways in which you can do this.
1) ARM can supply a number of standalone Verilog test benches to replay the patterns (.vec format). These were translated automatically by a script, from the crf/ctrm files, so you will simply use these instead of the supplied crf/ctrm files. You will need to edit each test bench to insert an instantiation of the device to be tested and connect up the JTAG signals as appropriate.
2) Users of the ModelGen tools can build a CRFtester similar to the one supplied with the Macrocell DSM, which reads in the CRF & CTRM files and applies them to a model of the core. This CRFtester would be simulator/OS specific, in the same way as the DSM.
3) You can use one of the other vector formats ARM supplies e.g. TSSI WGL, which you may already have a way to replay, as these are industry standards.
4) You could write a Perl (or C or shell) script to convert the ARM supplied patterns into your preferred format. This is actually not too difficult - there are only 4 inputs including the clock and a single output, with simple timing.
Article last edited on: 2008-09-09 15:47:35
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