|ARM Technical Support Knowledge Articles|
Applies to: ARM7TDMI
The processor always produces a byte address, but instructions are either words (4 bytes) or halfwords (2 bytes) and data can be any size. When word aligned instructions are fetched from memory, A[1:0] are undefined and when halfword instructions are fetched, A is undefined.
You should not rely on any particular value to be in these bits and the memory system should not look at those bits.
To give a little more detail about what actually happens (this is to help you understand the behavior - you don't need to know this, as the memory system should simply ignore these bits).
The ARM7TDMI will output some value on the A bus on every cycle. The internal control logic can choose from one of four address sources
So, in the case of a BX instruction, the ALU is used to calculate the address (it calculates r0 + 0) which gives a result with bit 0 set. This address appears on the A bus. The subsequent instruction fetches use the incrementer to simply add 2 to the previous address, so bit 0 stays set.
If after changing into thumb state, you do a word aligned load or store instruction, for example, you may see that after that, bit 0 of the address bus is clear and stays clear for subsequent instruction fetches.
Article last edited on: 2008-09-09 15:47:35
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