|ARM Technical Support Knowledge Articles|
Registers R0 - R14 (including banked registers) and SPSR (in all modes) are undefined after reset.
The Program Counter (PC/R15) will be set to 0x000000, or 0xFFFF0000 if the core has a VINITHI or CFGHIVECS input which is set high as the core leaves reset. This input should be set to reflect where the base of the vector table in your system is located.
The Current Program Status Register (CPSR) will indicate that the ARM core has started in ARM state, Supervisor mode with both FIQ and IRQ mask bits set. The condition code flags will be undefined. Please see the ARM Architecture Manual for a detailed description of the CPSR.
Article last edited on: 2008-09-09 15:47:35
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