How does the insertion of the AHB wrapper affect the performance of the ARM7TDMI?

Use of the ARM7TDMI AHB Wrapper results in the addition of a wait state for every NSEQ transfer in a burst. The AHB works off single rising edge of the clock, which makes it more synthesis friendly, and in general, AHB designs can be run at higher frequencies.

Below is an explanation of why the wait state is added.

Looking at the main events on the ARM7TDMI bus timing.

• nMREQ and SEQ (which indicate the cycle type) are driven from MCLK falling.
• A (the address bus) is driven from MCLK rising edges.
• DIN (the read data bus) is sampled on MCLK falling
• DOUT (the write data bus) is driven from MCLK falling to the next MCLK falling.

        ____      ____      ____
MCLK __|    |____|    |____|    |__
               _________
nMREQ --------<_________>----------
SEQ       
                   _________
A ----------------<_________>------
                        _________
DOUT ------------------<_________>-
                              ____
DIN -------------------------<____>
  

These signals are shown as tristate at times that are not relevant for the example, although they will still be driven by real values.

The majority of the system events are on MCLK falling edges, with only the A bus on MCLK rising.

So to put an AHB wrapper around this core we will invert HCLK (which has all events on rising edges) to generate MCLK. nMREQ/SEQ then generate HTRANS, DOUT becomes HWDATA, and DIN comes from HRDATA.

HADDR is the only problem. To be fully synchronous logic, we need to drive HADDR at the same time as HTRANS, but the A value is not valid until a half clock cycle later. So in the ARM7TDMI wrapper we add a wait state for all Non-Sequential accesses during which time we wait for A to be valid.

We can then use this valid A to drive HADDR. From then on, for Sequential cycles, we, inside the wrapper, calculate the next HADDR value (before the A bus is actually driven). We can see nMREQ and SEQ so we know if the address has to increment or not.

So this means we now have an AHB Bus Master which for most accesses does not need a wait state, and only for Non-Sequential accesses do we need a wait state so that we can, synchronous to HCLK rising, drive HADDR.

The AHB wrapper uses wait state for address synchronization. The wait states are only for Non-Sequential accesses and so will result in approximately 33% more cycles when accessing zero wait state memory.

Our experience has been that using this wrapper allows systems to be built at considerably higher clock speeds than would be possible otherwise (due to the lateness of the nMREQ/SEQ/A[] bus signals within the clock phase.