ARM Technical Support Knowledge Articles

When must the ABORT signal become active to signal a data abort or a prefetch abort?

Applies to: ARM7TDMI


The abort signal must be valid on the same clock edge as the data is read. The address appears during the clock high phase, on the cycle before the actual memory operation and stays valid throughout the clock low phase. The data (& abort signal) is read by the ARM on the next clock falling edge - if address pipelining is enabled, the address bus has already moved onto to the new value.

i.e what you need is

             _____       _____       _____
MCLK _____| |_____| |_____| |___
______ ___________ ___________ ________
A ______X__address__X___________X________
ABORT _____________________| |_____________
_____________________ _____ ___________
D _____________________X__D__X___________

You could do this is in a number of ways - e.g register or latch the value of the A[] bus before combinatorially decoding it, to ensure that the ABORT signal is generated in time to be sampled by the MCLK falling edge, but based on the A[] value of the previous cycle.

Article last edited on: 2008-09-09 15:47:35

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