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Applies to: ARM7TDMI
Chapter 6 of the ARM7TDMI Technical Reference Manual (1.8MB PDF) describes exactly what happens on each cycle of each instruction. Understanding exactly why there are or are not cycles of different types requires some knowledge of the instruction pipeline.
Essentially, an LDR takes 3 cycles to execute on the ARM7TDMI.
At this point, the LDR has completed and the next instruction moves into the execute pipeline stage. An LDR to any register except the pc will give a cycle type sequence like SEQ-NONSEQ-INTERNAL-SEQ. A LDR pc instruction will give a sequence like SEQ-NONSEQ-INTERNAL-NONSEQ-SEQ-SEQ
The STR requires only two cycles to execute. The first cycle calculates the address to be written to, while performing a fetch of a new instruction. The second cycle does the actual data write. No updating of registers with a data value is required, so unlike the LDR, a third 'writeback' cycle is not needed and so there are no internal cycles.
A STR instruction will give a sequence like
Other instructions which may give internal cycles are multiplies, data processing operations involving a register specified shift, load multiples, Swaps (SWP) and coprocessor instructions.
Article last edited on: 2008-09-09 15:47:35
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