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According to the TRM, nMREQ is only deasserted (to '1') preceding an Internal or coprocessor cycle. Why is it deasserted during an LDR instruction?

Applies to: ARM7TDMI

Answer

Chapter 6 of the ARM7TDMI Technical Reference Manual (1.8MB PDF) describes exactly what happens on each cycle of each instruction. Understanding exactly why there are or are not cycles of different types requires some knowledge of the instruction pipeline.

Essentially, an LDR takes 3 cycles to execute on the ARM7TDMI.

  • Cycle 1: Calculate the address to use. At the same time, we are performing a sequential instruction fetch from the pc address. The following cycle will use an address different from the pc address, so it will be non-sequential and the core indicates this (nMREQ=0, SEQ=0).
  • Cycle 2: Read the data value from the LDR address . The core knows that it does not need to perform a memory access on the next cycle, so it indicates an internal cycle (nMREQ=1, SEQ=0). The data is sampled on the falling edge of MCLK, right at the end of cycle 2, giving no time to do anything with it.
  • Cycle 3: In this cycle, the data read in cycle 2 is written back into the destination register. As the instruction does not change the pc and the LDR is about to complete, it knows that the next cycle will be a sequential instruction fetch from the pc address. During this cycle it outputs the pc value onto the A[] bus and sets nMREQ=0, SEQ=1 to indicate that the next cycle will be sequential.

At this point, the LDR has completed and the next instruction moves into the execute pipeline stage. An LDR to any register except the pc will give a cycle type sequence like SEQ-NONSEQ-INTERNAL-SEQ. A LDR pc instruction will give a sequence like SEQ-NONSEQ-INTERNAL-NONSEQ-SEQ-SEQ

The STR requires only two cycles to execute. The first cycle calculates the address to be written to, while performing a fetch of a new instruction. The second cycle does the actual data write. No updating of registers with a data value is required, so unlike the LDR, a third 'writeback' cycle is not needed and so there are no internal cycles.

A STR instruction will give a sequence like

SEQ(R)-NONSEQ(W)-NONSEQ(R).

Other instructions which may give internal cycles are multiplies, data processing operations involving a register specified shift, load multiples, Swaps (SWP) and coprocessor instructions.

See also:

Article last edited on: 2008-09-09 15:47:35

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