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What does the ARM7TDMI core read/write when using non aligned addresses?

Applies to: ARM7TDMI

Answer

When an ARM instruction fetch occurs, the two least significant bits in the address are undefined. Therefore an instruction fetch should always be considered to be aligned by the memory controller for the instruction to be fetched as expected, i.e. the memory system should ignore A[1:0] for an ARM instruction fetch. For Thumb instruction fetches, only A[0] should be ignored, because A[1] is now needed to indicate the half-word address.

Unaligned accesses can only take place for data loads or stores. In this case, address bits [1:0] indicate which byte is addressed.

Note: In general, the use of unaligned addresses should be avoided. Instead, the appropriate instructions should be used to load/store words (LDR/STR), half-words (LDRH/STRH) or bytes (LDRB/STRB). The behaviour of unaligned data loads and stores depends on the implementation ('unpredictable').

The following is a description of how the ARM7TDMI behaves. For a general description, please refer to the ARM Architecture Reference Manual.

Example:

Data Word   AA    BB    CC     DD     Endian Configuration
Bit:        31                 0
Byte        3     2     1      0      Little Endian
Address:    0     1     2      3      Big Endian
  

The following example shows the actions for a Little Endian system when the 2 least significant bits of the address are '10' (2), i.e. not word aligned:

For unaligned data stores:

a) Word store (STR): presented to the data bus: AA BB CC DD
A word store should generate a word aligned address. The word presented to the data bus is not modified even if the address is not word aligned.

The memory controller should ignore the two least significant bits of the address.

b) Half word store (STRH): presented to the data bus: CC DD CC DD
Register data bits [15:0] are duplicated across the data bus.

The memory controller should ignore the least significant bit of the address.

c) Byte store (STRB ): presented to the data bus: DD DD DD DD
Register data bits [7:0] are duplicated on all four byte lanes of the data bus. The memory controller needs all bits (incl. the two least significant bits) of the address.

For unaligned data read:

a) Word read (LDR ): read into register: CC DD AA BB
The whole word is read, but in the ARM core the bytes are rotated such that the byte which is addressed is stored on [7:0].

The memory controller should ignore the two least significant bits of the address.

b) half word read (LDRH): read into register: 00 00 AA BB
The selected half word is placed on the bottom [15:0] bits in the register and the remaining bits are filled with zeros by the core.

The memory controller should ignore the least significant bit of the address.

c) byte read (LDRB): read into register: 00 00 00 BB
The selected byte is placed on bits [7:0] in the destination register and the remaining bits of the register are filled with zeros by the core.

The memory controller needs all bits (incl. the two least significant bits) of the address.

In general:

The result of all half word loads or stores (issued as ARM or Thumb instructions) with a non-halfword aligned address will be unpredictable.

Important:

The memory controller must be able to handle word, half word and byte reads and writes!

If a memory controller is being designed to abort unaligned data transfer, it is essential that the signal nOPC is used to prevent instruction fetches from being aborted.

For further information, see the ARM7TDMI Technical Reference Manual (1.8MB PDF)

See also:

Article last edited on: 2008-11-05 13:56:13

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