How does Little / Big Endian mode affect aligned / unaligned addressing?

Applies to: ARM720T, ARM7TDMI, ARM920/922T, ARM940T, ARM9TDMI

Answer

The Endian configuration of your system has no effect if you always read / write words. It is only important when half words or bytes are read / stored.

The following table can be found in the ARM9TDMI Technical Reference Manual (Rev 3) (471KB PDF), section 3.6, and applies both to the ARM9TDMI and the ARM7TDMI (and processors containing these cores). It shows which bits of the data bus are read into the least significant bits of the destination register.

Table 1: Endian effects for 16-bit data fetches (LDRH)

A[1:0]	Little Endian	Big Endian
	(BIGEND=0)	(BIGEND=1)
00	D[15:0]	D[31:16]
10	D[31:16]	D[15:0]

Table 2: Endian effects for 8-bit data fetches (LDRB)

A[1:0]	Little Endian	Big Endian
	(BIGEND=0)	(BIGEND=1)
00	D[7:0]	D[31:24]
01	D[15:8]	D[23:16]
10	D[23:16]	D[15:8]
11	D[31:24]	D[7:0]

Example:

Data Word	AA	BB	CC	DD	Endian Configuration
Bit:	31			0
Byte Address:	3	2	1	0	Little Endian
Byte Address:	0	1	2	3	Big Endian

If last 2 address bits are [00] (aligned transfer):

Word read:	Little Endian	AA	BB	CC	DD
Word read:	Big Endian	AA	BB	CC	DD
Half word read:	Little Endian	00	00	CC	DD
Half word read:	Big Endian	00	00	AA	BB
Byte Read:	Little Endian	00	00	00	DD
Byte Read:	Big Endian	00	00	00	AA

If the last 2 address bits are [10] (unaligned transfer)

Word read:	Little Endian	CC	DD	AA	BB
Word read:	Big Endian	CC	DD	AA	BB
Half word read:	Little Endian	00	00	AA	BB
Half word read:	Big Endian	00	00	CC	DD
Byte Read:	Little Endian	00	00	00	BB
Byte Read:	Big Endian	00	00	00	CC

See also:

Article last edited on: 2008-09-09 15:47:35

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