ARM Technical Support Knowledge Articles

How does Little / Big Endian mode affect aligned / unaligned addressing?

Applies to: ARM720T, ARM7TDMI, ARM920/922T, ARM940T, ARM9TDMI


The Endian configuration of your system has no effect if you always read / write words. It is only important when half words or bytes are read / stored.

The following table can be found in the ARM9TDMI Technical Reference Manual (Rev 3) (471KB PDF), section 3.6, and applies both to the ARM9TDMI and the ARM7TDMI (and processors containing these cores). It shows which bits of the data bus are read into the least significant bits of the destination register.

Table 1: Endian effects for 16-bit data fetches (LDRH)

A[1:0] Little Endian Big Endian
00 D[15:0]D[31:16]
10 D[31:16]D[15:0]

Table 2: Endian effects for 8-bit data fetches (LDRB)

A[1:0] Little Endian Big Endian
00 D[7:0]D[31:24]
01 D[15:8]D[23:16]
10 D[23:16]D[15:8]
11 D[31:24]D[7:0]


Data Word AA BB CC DD Endian Configuration
Bit: 31     0  
Byte Address: 3210Little Endian
0123Big Endian

If last 2 address bits are [00] (aligned transfer):

Word read: Little EndianAABBCCDD
Half word read: Little Endian0000CCDD
Big Endian0000AABB
Byte Read: Little Endian000000DD
Big Endian000000AA

If the last 2 address bits are [10] (unaligned transfer)

Word read: Little EndianCCDDAABB
Half word read: Little Endian0000AABB
Big Endian0000CCDD
Byte Read: Little Endian000000BB
Big Endian000000CC

See also:

Article last edited on: 2008-09-09 15:47:35

Rate this article

Disagree? Move your mouse over the bar and click

Did you find this article helpful? Yes No

How can we improve this article?

Link to this article
Copyright © 2011 ARM Limited. All rights reserved. External (Open), Non-Confidential