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Applies to: ARM7TDMI
For the ARM7TDMI, there are essentially 3 different approaches to testing:
Conventional parallel test:
ARM supplies 10 sets of parallel test vectors, 27k vectors for ARM7TDMI, to test the functionality of the entire core. This test method requires access to all of the I/O signals of the cores, which sometimes might not be possible or feasible for an ARM core embedded in an ASIC.
Using serialised test vectors:
ARM provides 'serialised' test vectors for the ARM7TDMI core to test it through the JTAG port. For ARM7TDMI, this increases the number of vectors to over 900k. The advantage here is that only the 5 JTAG signals need to be accessible to the tester.
The TAP controller in the ARM processor core is a standard IEEE1149.1 compliant implementation. However, the scan cells used in the ARM7 core are not fully compliant, because they do not have an 'update' stage.
This technique uses ARM's standard on chip bus specifications, AMBA (Advanced Microcontroller Bus Architecture). If the users ASIC design implements AMBA, a 32 bit bus architecture, then it is possible to apply the AMBA test methodology to the core. The parallel test vectors have been partitioned into 32 bit words which can be applied to the core through the 32 bit test interface of the ASIC if the AMBA test methodology has been adopted.
The production test patterns for the ARM7TDMI have been converted into AMBA "TIC" (Test Interface Control) patterns which present about 100k test vectors, with generally only 3 extra pins required.
For ASIC designs using AMBA, this is the recommend approach.
Comparison of production vectors
Here is a vector count comparison between AMBA (TIC), Parallel, and Serialised (access through JTAG) production test vectors:
* The Debug and ICE test have a high proportion of pre-serialised sections.
Article last edited on: 2008-09-09 15:47:36
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