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Is an internal (I) cycle always followed by a sequential (S) cycle?

Applies to: ARM7TDMI


No, an I cycle will not always be followed by an S cycle. It can also be followed by a further I cycle, or by an N cycle. As pointed out in the ARM7TDMI Technical Reference Manual (1.8MB PDF), during an I cycle the ARM does not require any memory access. It will output the current PC value onto the address bus, as this is the most probable address it will require next. This allows the memory interface to see the address a cycle before it is required.

As explained in the TRM, this can be a benefit on some memory systems where a sequential address can be decoded (or the memory can be accessed) more quickly than a non-sequential address. As the address will remain the same between the I cycle and the S cycle, DRAM access can be started during the I cycle and then be completed in the S cycle, which may save 1 wait state.

However, in the situation where there is an internal cycle which changes the value of the pc (r15), the address output during the I cycle will not be correct. So the cycle after this will be a N cycle, using the new pc address. An instruction like LDR pc,[r0] or LDMFD sp!,{r0-r12,pc} would cause this. This type of instruction is often used to return from subroutines or C function calls, so this is quite a common case. Here, the memory decoder will look at the address during the I cycle and start to decode it. It will then sample nMREQ and SEQ (as it would normally) and see that the next cycle will be a N cycle and so it must ignore the address which was on A[] during the I cycle.

See also:

Article last edited on: 2008-09-09 15:47:36

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