|ARM Technical Support Knowledge Articles|
Applies to: ARM7TDMI
Interrupts are enabled by clearing the I (for IRQ) or F (for FIQ) flags in the CPSR with an MSR instruction. If an interrupt occurs as it is being enabled, the instruction following the MSR instruction will still be executed.
The reason is that the new flags are only available to the control logic at the end of the execution stage of the MSR instruction. The next instruction will have already been decoded and enters the execution stage of the instruction pipeline just as the flags are being changed.
Article last edited on: 2008-09-09 15:47:36
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