ARM Technical Support Knowledge Articles

What are the timing requirements of interrupts entering the ARM core?

Applies to: ARM7TDMI, ARM920/922T, ARM940T, ARM9TDMI


Interrupts can be synchronous or asynchronous, depending on the 'ISYNC' pin on the core. If interrupts are asynchronous, they will be synchronised before the interrupt is recognised.

When an interrupt is recognised by the ARM core, the core will finish executing the instruction which is currently in the execution stage of the ARM instruction pipeline before starting the interrupt sequence.

ARM has defined a standard programmers model of an interrupt controller, as part of our Reference Peripherals Specification . However, it is not necessary to implement the standard.

ARM defines timing arcs for setup/hold of nIRQ/nFIQ in both synchronous and asynchronous interrupt modes.

If running in synchronous interrupt mode, setup/hold timings must be met with respect to the clock.

Asynchronous setup/hold times define timings, which if met mean that the interrupt will be sampled by the core one cycle earlier than if not met. Timing violation warnings in a dynamic simulation can be ignored in asynchronous interrupt mode, and the relevant paths may be set as multicycle for STA.

See also:

Article last edited on: 2008-11-05 12:10:09

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