ARM Technical Support Knowledge Articles

Are the IRQ and FIQ interrupts level-sensitive?

Applies to: ARM1020/22E, ARM1026EJ-S, ARM1136, ARM720T, ARM7EJ-S, ARM7TDMI, ARM7TDMI-S, ARM920/922T, ARM926EJ-S, ARM940T, ARM946E-S, ARM966E-S, ARM9TDMI


Yes. The nIRQ and nFIQ inputs are active low, and level sensitive. They should be driven low and kept low until the interrupt service routine (interrupt handler) acknowledges the exception, then the interrupt request pin should be taken high again.

The normal way this works is that the system will have some interrupt controller external to the ARM core, which takes the interrupt sources and drives the nIRQ pin, (or nFIQ). The interrupt service routine would then read a memory mapped register in the interrupt controller hardware, to find out which interrupt source was active. It would then write to the interrupt controller register to clear the interrupt (causing the nIRQ pin to be deasserted) and in the case of a re-entrant interrupt handler, clear the CPSR 'I' bit.

See also:

Article last edited on: 2008-09-09 15:47:36

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