|ARM Technical Support Knowledge Articles|
When an exception occurs, the following happens inside the core:
* There are two interrupt disable bits, one for FIQ, one for IRQ. When ANY exception occurs, the disable interrupt bit is set, to disable IRQ. If the exception was FIQ or Reset, then the FIQ disable bit is also set.
The interrupt handler should clear the source of the interrupt before re-enabling further interrupts. One must be very careful when re-enabling interrupts in your handler that you have taken the appropriate steps to allow for re-entrant interrupts. For more information and example code, see the "Handling Processor Exceptions" chapter of the ADS Developer Guide (3MB PDF) or the RVCT Developer Guide (2MB PDF), or section 9.5 of the SDT 2.50 User Guide (7MB PDF) .
Article last edited on: 2008-09-09 15:47:36
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