What happens inside the ARM core when an exception occurs?

When an exception occurs, the following happens inside the core:

1. The CPSR is copied to the SPSR of the mode being entered.
2. The CPSR bits are set as appropriate to the mode being entered, the core is set to ARM state, and the relevant interrupt disable flags are set*.
3. The appropriate set of banked registers are banked in.
4. The return address is stored to the link register (of the relevant mode)
5. The PC is set to the relevant vector address.

* There are two interrupt disable bits, one for FIQ, one for IRQ. When ANY exception occurs, the disable interrupt bit is set, to disable IRQ. If the exception was FIQ or Reset, then the FIQ disable bit is also set.

The interrupt handler should clear the source of the interrupt before re-enabling further interrupts. One must be very careful when re-enabling interrupts in your handler that you have taken the appropriate steps to allow for re-entrant interrupts. For more information and example code, see the "Handling Processor Exceptions" chapter of the ADS Developer Guide (3MB PDF) or the RVCT Developer Guide (2MB PDF), or section 9.5 of the SDT 2.50 User Guide (7MB PDF) .

See also:

• ADS Developer Guide (3MB) (DUI 0056D)
• RVCT Developer Guide (2MB) (DUI 0203G)
• SDT 2.50 User Guide (7MB) (DUI 0040D)
• Is there a priority scheme for exceptions?