|ARM Technical Support Knowledge Articles|
Upon entry to the IRQ exception handler, the 'I' bit is set and further interrupts (IRQ) cannot be recognised by the core until the handler explicitly re-enables further interrupts by writing to the CPSR. Upon entry to the FIQ exception handler, both the 'I' bit and the 'F' bit is set and further interrupts, fast or normal, cannot be recognised by the core until the handler explicitly re-enables further interrupts by writing to the CPSR.
The IRQ/FIQ handler should not re-enable interrupts until it has acknowledged the interrupt to whatever is driving the nIRQ/nFIQ input, otherwise the core will immediately re-enter the interrupt handler.
Note: Pipeline Hazard
Due to a pipeline hazard on later ARM cores, you should always ensure that there is plenty of time between the acknowledgement and the re-enabling of the interrupts.
Consider the following piece of ARM code:
STR r1, [r0] ; ack. interrupt by writing to the interrupt controller
MSR cpsr_c, r2 ; re-enable interrupts
On the ARM9TDMI and later cores, the STR write to external memory may occur as little as one CLK cycle before the interrupts are re-enabled by the MSR instruction. Hence if the interrupt controller takes longer than one ARM CLK cycle to clear the interrupt signals into the core, it will re-enter the interrupt exception handler.
For this reason, ARM recommends that programmers acknowledge interrupts at the very beginning of the exception handler. The exception handler should not re-enable interrupts until the very end of the exception handler unless nested interrupts are being used. If nested interrupts are being used, programmers should ensure that there is some padding between the acknowledge and re-enable of interrupts to allow time for the interrupt signals to change.
Article last edited on: 2008-09-09 15:47:36
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