ARM Technical Support Knowledge Articles

Are there are any special considerations when memory mapping hardware registers?

Applies to: ARM1020/22E, ARM1026EJ-S, ARM1136, ARM720T, ARM7EJ-S, ARM7TDMI, ARM7TDMI-S, ARM920/922T, ARM926EJ-S, ARM940T, ARM946E-S, ARM966E-S, ARM9TDMI


In this FAQ we name the system data bus D[31:0], as it is named on the ARM7TDMI. This name will be different for ASB and AHB implementations.

It is strongly recommended that ARM based designs align memory mapped hardware registers on word (32-bit) boundaries, rather than sub-word boundaries. The main reason for this is to make the hardware interface easier to implement.

When reading 8 or 16 bit values from a peripheral the data must be presented on the correct byte lane. For example when the ARM reads an 8-bit register at address 0x2 it expects the data to be presented on data lines D[23:16]. This means that hardware is needed to route the data from the registers appropriately. If the ARM is in big endian mode then this will be different.

If all memory-mapped registers are on word boundaries then the data can be presented on D[7:0] or D[15:0] and no byte lane steering hardware is required. Writes do not matter so much because the ARM will write a byte on all byte lanes or a half-word on both halves to make interfacing easier.

In general, the hardware must ensure that 8, 16 and 32 bit accesses to memory and registers work correctly and that data is presented on the correct byte lane associated with the size and address of the transfer.

See also:

Article last edited on: 2008-09-09 15:47:36

Rate this article

Disagree? Move your mouse over the bar and click

Did you find this article helpful? Yes No

How can we improve this article?

Link to this article
Copyright © 2011 ARM Limited. All rights reserved. External (Open), Non-Confidential