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Applies to: ARM720T
ARM720T rev 0-3 contain an ARM7TDMI, caches, an MMU and an ASB interface (which may be connected to an AHB system with a special wrapper). The core is clocked by BCLK and FCLK and both edges of both clocks are used.
ARM720T rev 4 contains an ARM7TDMI-S, with a different cache structure and external AHB interface. Only the rising edge of HCLK is used at the bus interface, but the ARM720T still uses both edges of the clock within the core, and not having a 50/50 duty cycle will impact the speed of the core.
Article last edited on: 2008-09-09 15:47:36
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