There are several things which can cause problems.
- You need to ensure FCLK is correctly driven, as addressed in this FAQ.
- You need to ensure that the decoder never adds decode cycles during the 720T test. You also need to ensure that the address given in the test vectors corresponds to the memory mapped address of the ARM. This typically requires changes to the first 2 lines of the supplied TIF files.
- If BWAIT is being used (to add decode/wait states), it will not work when testing the ARM720T. Its test mode state machine does not take decode cycles into account. This often happens because the TIC is generating non-sequential cycles and the decoder automatically inserts decode cycles in this case.
If you are using the supplied ARM720T vectors in the Micropack 2.0 EASY world, you'll need to change the first two lines of each .tif file, as follows:
A 50000000 ; or possibly some
A 50000169 ; other address e.g c0000000
This is required because:
- We need to use the AMBA Test Control vector to change the types of cycle that the TIC produces. AMBA ASB control vectors are described in the rev 2.0 AMBA spec on page 6-26.
- Bit 8 of the vector selects a feature called SeqOnly which essentially forces the TIC to only produce SEQ type cycles. This fixes a problem with the test mode if DSEL is deasserted during decode cycles. Decode cycles can only occur on non-sequential cycles, so we simply tell the TIC not to generate these.
It may be necessary when performing RTL simulation to delay some signals with respect to the clock edge. Some customers have reported that their simulation only behaved correctly when DSEL, BWRITE & BD were delayed (e.g using VHDL 'after 1ns' type statements) slightly with respect to the clock edge.