ARM Technical Support Knowledge Articles

Does the ARM720T with the cache disabled behave like an ARM7TDMI?

Applies to: ARM720T


No. The ARM720T will run much more slowly with the cache off than the ARM7TDMI would do in the same circumstances. All of the design optimization is targeted at improving the performance with the cache ON - as this is how the device is intended to be used.

When the ARM720T cache is disabled, each instruction (a single read which misses in the cache) will cost up to 4 I cycles (depending upon clock mode), followed by an S cycle. All the following steps are required in the worst case.

  • 1 cycle cache miss BCLK if fastbus mode, FCLK otherwise
  • 1 internal cycle BCLK if fastbus mode, FCLK otherwise, used for some internal decoding
  • 1 S cycle fetch BCLK cycle to perform the word fetch

If you had selected synchronous or asychronous mode, there might be further cycle penalties associated with switching between BCLK & FCLK.

This is significantly slower than you would see with the ARM7TDMI.

The ARM720T will only operate efficiently when the cache & MMU are enabled.

Article last edited on: 2008-09-09 15:47:36

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