|ARM Technical Support Knowledge Articles|
Applies to: ARM720T
This FAQ assumes you have read the MMU datasheet description and know enough assembly language to turn the cache, MMU & write buffer on. A description of how the level 1 descriptors must be setup follows.
Assuming you simply want a flat mapping from virtual address to physical address, with the whole space mapped in 1MB sections to keep the page table as small as possible and with read/write access to all areas, the following is necessary:
You need to generate 4K entries, starting from the TTB address, which must lie on a 16K boundary. Each entry must look like this:
Bits 31:20 = Base address for the section (i.e 0MB for the first entry, 1MB for the second and so on)
Bits 19:12 = Don't care - should be 0
Bits 11:10 = Access Permission - write as 11 to allow all accesses
Bit 9 = Should be 0
Bits 8:5 = Domain 0 - make it 0 for simplicity as you did above.
Bit 4 = Must be '1'
Bits 3:2 = '11' Cacheable and bufferable.
Bits 1:0 Must be '10' for a section
So, the first entry will be 0x00000C1E, the next entry will be 0x00100C1E, then 00200C1E, all the way up to FFF00C1E.
Article last edited on: 2008-09-09 15:47:36
Did you find this article helpful? Yes No
How can we improve this article?